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NT7651
PRELIMINARY Features
! Single-chip LCD controller/driver ! 2-line display of up to 16 characters + 160 icons, 1-line display of up to 32 characters + 160 icons, or 1-line display of up to 16 characters + 80 icons ! 5 x 7 character format plus cursor; 5 x 8 for user defined symbols ! Icon mode: Reduced current consumption while displaying icons only ! On-chip: DC-DC converter generation of LCD supply voltage, independent of VDD Temperature compensation of on-chip generated VLCD: -8 t -12 mV/K at 5.0 V (programmable by instruction) Generation of intermediate LCD bias voltages Oscillator requires no external components (external clock also possible). ! Versatile display functions provided on chip: Clear display, Return home, Entry mode set, Display control, Cursor /display shift, Character blink, Icon blink, Screen configuration, Icon display control. ! Character Generator ROM: 240 characters (240 x 5 x 8 bits). ! Character Generator RAM: 16 characters (16 x 5 x 8 bits); 4 characters used to drive 160 icons, 8 characters used if icon blink feature is used in application. ! Display Data RAM: 80 characters (80 x 8 bits) ! 18 common and 80 segment outputs ! Three duty factors selected by program: 1/2 duty for icon only mode 1/9 duty for single line operation 1/18 duty for normal operation ! Logic supply voltage range: Chip may be driven with two battery cells. VDD1 = 1.5 to 3.5 V ! High voltage generator supply voltage range: VDD2 = 2.2 to 3.5V ! Display supply voltage range: VLCD = 4.5 to 6.5 V ! Very low current consumption (VDD=3.0V): Icon mode: < 160 A (DC-DC on) Power-down mode: < 2 A. Normal mode: < 180 A (DC-DC on) ! 4 or 8-bit parallel bus and 2-wire I2C-bus interface ! CMOS compatible ! Available in COG FORM
LCD controller/driver 16Cx2 characters + 160 icons
General Description
The NT7651 is a low power CMOS LCD controller and driver designed to drive a dot matrix LCD display of 2-line by 16 or 1-line by 32 characters with 5 x 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and lower system current consumption. The NT7651 interfaces to most microcontrollers via a 4 or 8-bit bus or via the 2-wire I2C-bus. The chip contains a character generator and displays alphanumeric character.
Preliminary
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Block Diagram
SEG1~80 COM1~18 & COM17DUP & COM18DUP
80
SEGMENT DRIVERS
18
COMMON DRIVERS
VLCD1
BIAS VOLTAGE GENERATOR
80
18
DATA LATCHES
SHIFT REGISTER 18 BIT
80 VLCD2
VLCD GENERATOR SHIFT REGISTER 5 x 16 BIT
VDD1 VDD2,3
5
CURSOR & DATA CONTROL
VSS1 5 VSS2
CGRAM (16 x 8 x 5) 16 CHARACTERS CGROM (240 x 8 x 5) 240 CHARACTERS
PD RESET 8
DDRAM ( 80 x 8) 80 CHARACTERS OSCILLATOR
OSC
7
7
ADDERSS COUNTER (AC) TIMING GENERATOR
T1 T2 T3 T4 T5 T6
DATA REGISTER (DR)
7
7
INSTRUCTION DECODER
7
DISPLAY ADDRESS COUNTER
8
INSTRUCTION REGISTER (IR)
BUSY FLAG
8
8
I/O BUFFER
DB0/SA0
DB[1:7]
E
R/W
RS
SCL
SDA
Preliminary
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Pad Configuration
82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63
SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] COM[17]DUP COM[8] COM[7] COM[6] COM[5] COM[4] COM[3] COM[2] COM[1] COM[17] 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
SEG[70] SEG[69] SEG[68] SEG[67] SEG[66] SEG[65] SEG[64] SEG[63] SEG[62] SEG[61] SEG[60] SEG[59] SEG[58] SEG[57] SEG[56] SEG[55] SEG[54] SEG[53] SEG[52] SEG[51] SEG[50] SEG[49] SEG[48] SEG[47] SEG[46] SEG[45] SEG[44] SEG[43] SEG[42] SEG[41] SEG[40] SEG[39] SEG[38] SEG[37] SEG[36] SEG[35] SEG[34] SEG[33] SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] SEG[12] SEG[11]
83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142
NT7651
Preliminary
SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] SEG[1] COM[18]DUP COM[16] COM[15] COM[14] COM[13] COM[12] COM[11] COM[10] COM[9] COM[18]
143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162
VLCD2 VLCD2 VLCD2 VLCD2 VLCD2 VLCD2 VLCD1 VLCD1 VLCD1 VLCD1 VLCD1 VLCD1 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 T3 T2 T1 E VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD2 VDD2 VDD1 VDD1 VDD1 VDD1 OSC OSC T4 T5 DB[7] DB[6] DB[5] DB[4] DB[3] DB[2] DB[1] DB[0]/SA0 T6 RS R/W SDA SDA PD RESET DUMMY SCL SCL
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82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63
SEG[71] SEG[72] SEG[73] SEG[74] SEG[75] SEG[76] SEG[77] SEG[78] SEG[79] SEG[80] COM[17]DUP COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] COM[17] 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
SEG[70] SEG[69] SEG[68] SEG[67] SEG[66] SEG[65] SEG[64] SEG[63] SEG[62] SEG[61] SEG[60] SEG[59] SEG[58] SEG[57] SEG[56] SEG[55] SEG[54] SEG[53] SEG[52] SEG[51] SEG[50] SEG[49] SEG[48] SEG[47] SEG[46] SEG[45] SEG[44] SEG[43] SEG[42] SEG[41] SEG[40] SEG[39] SEG[38] SEG[37] SEG[36] SEG[35] SEG[34] SEG[33] SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] SEG[12] SEG[11]
83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142
NT7651R
Preliminary
SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] SEG[1] COM[18]DUP COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[18]
143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162
VLCD2 VLCD2 VLCD2 VLCD2 VLCD2 VLCD2 VLCD1 VLCD1 VLCD1 VLCD1 VLCD1 VLCD1 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 T3 T2 T1 E VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD2 VDD2 VDD1 VDD1 VDD1 VDD1 OSC OSC T4 T5 DB[7] DB[6] DB[5] DB[4] DB[3] DB[2] DB[1] DB[0]/SA0 T6 RS R/W SDA SDA PD RESET DUMMY SCL SCL
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Pad Description
Pad No. NT7651 23~26 27~34 39~44 45~50 51~56 57~62 NT7651R 23~26 27~34 39~44 45~50 51~56 57~62 VDD1 VDD2,3 VSS1 VSS2 VLCD1 VLCD2 P P P P P P Logic supply voltage. Supply voltage for the high voltage generator. (Always put VDD2 = VDD3). Ground pad for all except the high voltage generator. Ground pad for the high voltage generator. This input used for the generation of the LCD bias levels. VLCD output pad. If VLCD is generated internally, this pad must be connected to VLCD1. If in the application an external VLCD is used, then the VLCD2 pin must be left open-circuit. The parallel interface data bus clock input. It is set HIGH to signal the start of a read or write operation and data in or out of the chip on falling edge of the clock. When I2C-bus is used, the parallel interface pad E must be at logic 0. Test pads. T1 andT2 must be connected to VSS1, Others are left open-circuit and are not user accessible. No connect for user. Designation I/O Description
35
35
E
I
36 37 38 20 19 10 63 64~71 72 73~152 153 154~161 162 1,2 4 5 6,7
36 37 38 20 19 10 63 71~64 72 73~152 153 161~154 162 1,2 4 5 6,7
T1 T2 T3(4) T4(RC) T5(M) T6(D) COM[17] COM[1:8] COM17DUP SEG[80:1] COM18DUP COM[16:9] COM[18] SCL RESET PD SDA
I I I I I I O O O
LCD common driver outputs. COM17 has two pads COM17 and COM17DUP. LCD segment driver outputs. LCD common driver outputs. COM18 has two pads COM18 and COM18DUP. I2C-bus serial clock input. When the parallel bus is used, It must be connected to VSS1 or VDD1. External power-on reset input. (High active) Chip power-down mode selects input. Normal operation PD =0. I2C-bus serial data input/output. When the parallel bus is used, It must be connected to VSS1 or VDD1. Data read/write selects input. Read ( R/ W =1) or write ( R/ W =0). Internal pull-up. Register selects signal input. Internal pull-up. RS = 0, selects the instruction register for write and the busy flag and address counter for read. RS =1, selects the data register for both read and write. Bidirectional data bus (3-state). In 4-bit operations, It must be left open-circuit. It has its own internal pull-up. In the I2C-bus operation, shared with alternative function input (SA0), It can allow connecting two NT7651 drivers to the same I2C-bus. 5/38 Ver 0.21
I I I I/O
8
8
R/ W
I
9
9
RS
I
DB[0] 11 11 SA0
I/O I
Preliminary
NT7651
Pad No. NT7651 NT7651R Bidirectional data bus (3-state). DB7 may be used as the busy flag, In 4-bit operations the 4 higher order lines DB7 toDB4 are used, DB3 to DB0 must be left open-circuit. Each data line has its own internal pull-up. Oscillator or external clock input. When the on-chip oscillator is used this pad must be connected to VDD1. Left open-circuit or connected to VSS1. Designation I/O Description
12~18
12~18
DB[1:7]
I/O
21,22 3 Total 162 pads
21,22 3
OSC DUMMY
I -
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Functional Description
1. LCD supply voltage generator The LCD supply voltage may be generated on-chip. Two internal 6-bit registers control the voltage generator: VA and VB. The nominal LCD operating voltage at room temperature (TREF =27C) is given by the relationship: VLCD = (integer value of register x 0.082) + 1.82 Integer value of register programming ranges: 1 to 63. Operating voltage ranges: 1.902 to 6.986 V. Notice: Values producing more than 6.5 V at operating temperature are not allowed. Operation above this voltage may damage the device. When programming the operating voltage the VLCD temperature coefficient must be taken into account. Values below 4.5 V are below the LCD display bias levels threshold voltage and are therefore not allowed. Value 0 for VA and VB switches the generator off. Usually register VA is programmed with the voltage for character mode and register VB with the voltage for icon mode. Table 1 Bias levels for the different duty Duty 1:18 1:9 1:2 VSS = 0V. 3. Oscillator The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC pad must be connected to VDD. Only in the power-down state is the clock allowed to be stopped (OSC connected to VSS), otherwise the LCD is frozen in a DC state. 4. Power-on reset It must be reset externally. This is an internal synchronous reset that requires 3 OSC cycles to be executed after release of the external reset signal. If no external reset is performed, the chip might start-up in an unwanted state. The external reset is active HIGH. 5. Power-down mode The chip can be put into power-down mode where all static currents are switched off (no internal oscillator, no bias level generation and all LCD outputs are internally connected to VSS) when PD = 1. To ensure IDD <1 A, the parallel bus pads DB7 to DB0 should be connected to VDD; RS and R/ W to VDD or left open-circuit. During power-down, information in the RAMs and the Chip State are preserved. Instruction execution during power-down is possible when pad OSC is externally clocked. Recovery from power-down mode: PD back to logic 0, if necessary OSC back to VDD and send a `display control' instruction. 6. Busy flag The busy flag indicates the internal status of the chip. Logic 1 indicates that the chip is busy and further instructions will not be accepted. The busy flag is output to pad DB7 when RS = 0 and R/ W = 1. Instructions should only be written after checking that the busy flag is at logic 0 or waiting for the required number of cycles. Bias Levels 5 5 4 V1 VLCD VLCD VLCD V2 VLCD x 3/4 VLCD x 3/4 VLCD x 2/3 V3 VLCD x 1/2 VLCD x 1/2 VLCD x 2/3 V4 VLCD x 1/2 VLCD x 1/2 VLCD x 1/3 V5 VLCD x 1/4 VLCD x 1/4 VLCD x 1/3 V6 VSS VSS VSS When VLCD is generated on-chip the VLCD pads should be decoupled to VSS with a suitable capacitor. The generated VLCD is independent of VDD and is temperature compensated. When the generator is switched off an external voltage may be supplied at connected pads VLCD1. VLCD1 may be higher than VDD. The LCD supply voltage generator ensures that, as long as VDD is in the valid range (2.2 to 3.5V), the required peak voltage VLCD = 6.5V can be generated at any time. 2. LCD bias voltage generator The intermediate bias voltages for the LCD display are also generated on-chip. The optimum value of VLCD depends on the LCD duty, the LCD threshold voltage (VTH) and the number of bias levels. Using a 5-level bias scheme for 1: 18 maximum duty allows VLCD < 5 V for most LCD liquids. The intermediate bias levels for the different duty are shown in Table 1. These bias levels are automatically set to the given values when switching to the corresponding LCD duty.
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7. Registers The NT7651 has two 8-bit registers, an Instruction Register (IR) and a Data Register (DR). The Register Select signal (RS) determines which register will be accessed. The instruction register stores instruction codes and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM). The instruction register can be written to but not read from by the system controller. The data register temporarily stores data to be read from the DDRAM and CGRAM. When reading, data from the DDRAM or CGRAM corresponding to the address in the instruction register is written to the data register prior to being read by the `read data' instruction. 8. Address Counter (AC) The address counter assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the commands `set CGRAM address' and `set DDRAM address'. After a read/write operation the address counter is automatically incremented or decremented by 1. Table 2 Address space and wrap-around operation MODE Address space Read/write wrap-around (moves to next line) Display shift wrap-around (stays within line) 1 x 32 00 to 4F 4F to 00 4F to 00 2 x 16 00 to 27; 40 to 67 27 to 40; 67 to 00 27 to 00; 67 to 40 1 x 16 00 to 27 27 to 00 27 to 00 The address counter contents are output to the bus (DB6 to DB0) when RS = 0 and R/ W =1. 9. Display Data RAM (DDRAM) The DDRAM stores up to 80 characters of display data represented by 8-bit character codes. RAM locations that are not used for storing display data can be used as general purpose RAM. The basic RAM to display addressing scheme is shown in Figure 2. With no display shift the characters represented by the codes in the first 32 RAM locations starting at address 00H in line 1 are displayed. Figure 3 and Figure 4 show the display mapping for right and left shift respectively. When data is written to or read from the DDRAM wrap-around occurs from the end of one line to the start of the next line. When the display is shifted each line wraps around within itself, independently of the others. Thus all lines are shifted and wrapped around together. The address ranges and wrap-around operations for the various modes are shown in Table 2.
10. Character Generator ROM (CGROM) The Character Generator ROM generates 240 character patterns in a 5 x 8 dot format from 8-bit character codes. Figure 5, Figure 6 shows the character set that is currently implemented.
11. Cursor control circuit The cursor control circuit generates the cursor (underline and/or cursor blink as shown in Figure 1) at the DDRAM address contained in the address counter. When the address counter contains the CGRAM address the cursor will be inhibited.
5 x 7 dot character font
cursor Cursor display example Blink display example
Figure 1 Cursor and blink display examples.
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12. Character Generator RAM (CGRAM) Up to 16 user defined characters may be stored in the Character Generator RAM. Some CGRAM characters (see Figure 10) are also used to drive icons (8 if icons blink and both icon commons are used in the application; 4 if no blink but both icon commons are used in the application; 0 if no icons are driven by the icon commons). The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM. Table 3 shows the addressing principle for the CGRAM. Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor. Data in the 8th position will appear in the cursor position. Character pattern column positions correspond to CGRAM data bits 0 to 4. CGRAM data = logic 1 corresponds to selection for display. Only bits 0 to 5 of the CGRAM address are set by the `set CGRAM address' command. Bit 6 can be set using the `set DDRAM address' command in the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the `read busy flag and address counter' command.
Table 3 Relationship between CGRAM addresses data and display patterns Character codes (DDRAM data) Higher
7 0 6 0 5 0
CGRAM address Order bits
5 0 4 0 3 0 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 6 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4 3
CGRAM data (example) Lower Character patterns
2 1 0
Order bits
4 0 3 0 2 0 1 0
Lower Higher
0 0
Character code
4 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0 3 1 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0 2 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 1 0 1 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0
Cursor position
0
0
0
0
0
0
0
1
0
0
0
1
Cursor position
0
0
0
0
0
0
1
0
0
0
1
0
0 0
0 0
0 0
0 0
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
Preliminary
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1
2
3
4
5
30 31 32
non-display DDRAM adress 4D 4E 4F
DDRAM address
00 01 02 03 04
1D 1E 1F 20 21 22 23 24
1-line display
non-display DDRAM adress 1 2 3 4 5 14 15 16 0D 0E 0F 10 11 12 13 14 25 26 27 00 01 02 03 04
Line1
DDRAM address
40 41 42 43 44 1 2 3 4 5
2-line display/duty 1/9 mode
4D 4E 4F 50 51 52 53 54 14 15 16 65 66 67
Line2
Figure 2 DDRAM to display mapping: no shift.
1
2
3
4
5
30 31 32 1C 1D 1E
DDRAM address
4F 00 01 02 03
1-line display
1 2 3 4 5 14 15 16 0C 0D 0E
27 00 01 02 03
Line1
DDRAM address
1
2-line display/duty 1/9 mode
67 40 41 42 43 2 3 4 5 4C 4D 4E 14 15 16
Line2
Figure 3 DDRAM to display mapping: right shift.
1
2
3
4
5
30 31 32 1E 1F 20
DDRAM address
01 02 03 04 05
1-line display
1 2 3 4 5 14 15 16 0E 0F 10
01 02 03 04 05
Line1
DDRAM address
1
2-line display/duty 1/9 mode
41 42 43 44 45 2 3 4 5 4E 4F 50 14 15 16
Line2
Figure 4 DDRAM to display mapping: left shift.
Preliminary
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lower 4bits
upper 4bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
xxxx 0000
1
xxxx 0001
2
xxxx 0010
3
xxxx 0011
4
xxxx 0100
5
xxxx 0101
6
xxxx 0110
7
xxxx 0111
8
xxxx 1000
9
xxxx 1001
10
xxxx 1010
11
xxxx 1011
12
xxxx 1100
13
xxxx 1101
14
xxxx 1110
15
xxxx 1111
16
Figure 5 Character set `stand code R' in CGROM.
Preliminary
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lower 4bits
upper 4bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
xxxx 0000
1
xxxx 0001
2
xxxx 0010
3
xxxx 0011
4
xxxx 0100
5
xxxx 0101
6
xxxx 0110
7
xxxx 0111
8
xxxx 1000
9
xxxx 1001
10
xxxx 1010
11
xxxx 1011
12
xxxx 1100
13
xxxx 1101
14
xxxx 1110
15
xxxx 1111
16
Figure 6 Character set `stand code S' in CGROM .
Preliminary
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13. LCD common and segment drivers The NT7651 contains 18 common and 80 segment drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. COM17 and COM18 drive the icon common. The bias voltages and the timing are selected automatically when the number of lines in the display is selected. fFRAME =fOSC/2880, Figure 7 to Figure 9 show typical waveforms. Unused outputs should be left unconnected.
1
18 1
18
V1 V2 COM1 V3/V4 V5 V6 V1 V2
COM9 V3/V4
V5 V6 V1 V2 COM2 V3/V4 V5 V6 V1 V2 V3/V4 SEGn V5 V6 V1 V2
SEGn+1 V3/V4
V5 V6
no display
V1 V2 V3/V4 COM1 V5 0V + SEGn -V5 -V3/V4 -V2 -V1
display
V1 V2 V3/V4 COM1 V5 0V + SEGn+1 -V5 -V3/V4 -V2 -V1
fFRAME
Figure 7 1/18 duty LCD waveforms (Characters + 160 icons mode).
Preliminary
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1
9
1
9
V1 V2
COM1 V3/V4
V5 V6 V1 V2 COM2 V3/V4 V5 V6 V1 V2 COM3 V3/V4 V5 V6 V1 V2
COM17
SEGn V3/V4
V5 V6 V1 V2 SEGn+1 V3/V4 V5 V6
no display display
V1 V2 V3/V4 COM1 V5 0V + SEGn -V5 -V3/V4 -V2 -V1
V1 V2 V3/V4 COM1 V5 0V + SEGn+1 -V5 -V3/V4 -V2 -V1
fFRAME
Figure 8 1/9 duty LCD waveforms (Characters + 80 icons mode).
Preliminary
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COM17
V1 V2/V3 V4/V5 V6 V1 V2/V3 V4/V5 V6 V1 V2/V3 V4/V5 V6 V1 V2/V3 V4/V5 V6 V1 V2/V3 V4/V5 V6 V1 V2/V3 V4/V5 V6 V1 V2/V3 V4/V5 V6 V1 V2/V3 V4/V5 0V -V4/V5 -V2/V3 -V2 V1 V2/V3 V4/V5 0V -V4/V5 -V2/V3 -V2 V1 V2/V3
COM18 COM1 ~ COM16 SEGn
SEGn+1
SEGn+2
SEGn+3
no display display
COM17 + SEGn
COM17 + SEGn+1
COM1~16 V4/V5 0V + -V4/V5 SEGn
-V2/V3 -V2
fFRAME
Figure 9 1/2 duty LCD waveforms (Icon mode).
Preliminary
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Initial State
The NT7651 must be reset externally when power is turned on. The reset executes a `clear display', requiring 165 oscillator cycles. After the reset the chip has the state shown in Table 4. Table 4 State after reset Step 1 2 Function Clear display Entry mode set I/D= 1 S=0 D=0 3 Display control C=0 B=0 DL= 1 4 Function set M=0 H=0 SL=0 5 6 7 8 9 10 11 Default address pointer to DDRAM Busy Flag (BF) indicates Icon control Display/screen configuration VLCD temperature coefficient Set VLCD I2C-bus interface reset BF = 1 IM,IB=00 L=0; P = 0; Q=0 TC1= 0; TC2=0 VA =0; VB =0 The busy state lasts 2 ms, until initialization ends. The chip may also be initialized by software. see Table 5 and Table 6 icons/icon blink disabled default configurations default temperature coefficient VLCD generator off +1 (increment) No shift Display off Cursor off Cursor character blink off 8-bit interface 1-line display Normal instruction set Duty 1/18 mode Control bit state Remarks
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Table 5 Initialization by instruction, 8- bit interface Step Power-on or unknown state Wait 2ms after external reset has been applied RS R/ W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set (interface is 8bits long). BF cannot be checked before this instruction. 0 0 0 0 1 1 X X X X X = don't care. Wait 2ms 0 0 0 0 1 1 X X X X The waiting time between instructions is the specified instruction time. (See Table 9) Function set (interface is 8bits long) BF can be checked after the following instructions. X = don't care. Function set (interface is 8bits long), specify the number of display lines display off clear display entry mode set Description
Wait more than 40s 0 0 0 0 1 1 X X X X
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 0 0 0
1 0 0 0
0 1 0 0
M 0 0 1
SL 0 0 I/D
H 0 1 S
Instruction initialization ends
Table 6 Initialization by instruction, 4- bit interface Step Power-on or unknown state Wait 2ms after external reset has been applied RS 0 R/ W 0 DB7 0 DB6 0 DB5 1 DB4 1 Function set (interface is 8bits long). BF cannot be checked before this instruction. Description
Wait 2ms 0 0 0 0 1 1 The waiting time between instructions is the specified instruction time. (See Table 9) Function set (interface is 8bits long) BF can be checked after the following instructions. Function set (interface to 4bits long) Function set (interface is 4bits long), specify the number of display lines display off clear display entry mode set
Wait more than 40s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 M 0 0 0 0 0 1 1 1 1 SL 0 0 0 0 0 I/D 1 0 0 H 0 0 0 1 0 S
Instruction initialization ends
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Instructions
Only the Instruction Register (IR) and the Data Register (DR) can be directly controlled by the MPU. Before internal operation, control information is stored temporarily in these registers, to allow interfacing to various types of MPUs that operate at different speeds or to allow interface to peripheral control ICs. The NT7651 operation is controlled by the instructions shown in Table 9 together with their execution time. During internal operation, no instructions other than the `read busy flag' and `read address' instructions will be executed. Because the busy flag is set to a logic 1 while an instruction is being executed, check to ensure it is a logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in Table 9. Standard instruction details explain H = 0, sets the chip into standard instruction set mode. 1. Clear display `Clear display' writes character code A0H into all DDRAM addresses (the character pattern for character code A0H must be a blank pattern), sets the DDRAM address counter to logic 0 and returns the display to its original position, if it was shifted. Thus, the display disappears and the cursor or blink position goes to the left edge of the first display line. Sets entry mode I/D = 1 (increment mode). S of entry mode does not change. The instruction `clear display' requires extra execution time. This may be allowed by checking the Busy Flag (BF) or by waiting until the 165 clock cycles have elapsed. 2. Return home `Return home' sets the DDRAM address counter to logic 0 and returns the display to its original position if it was shifted. DDRAM contents do not change. The cursor or blink position goes to the left of the first display line. I/D and S of entry mode do not change. 3. Entry mode set (a) I/D When I/D = 1 (0) the DDRAM or CGRAM address increments (decrements) by 1 when data is written into or read from the DDRAM or CGRAM. The cursor or blink position moves to the right when incremented and to the left when decremented. The cursor underline and cursor character blink are inhibited when the CGRAM is accessed. (b) S When S = 1, the entire display shifts either to the right (I/D = 0) or to the left (I/D = 1) during a DDRAM write. Thus it appears as if the cursor stands still and the display moves. The display does not shift when reading from the DDRAM, or when writing to or reading from the CGRAM. When S = 0, the display does not shift. 4. Display control (and partial power-down mode) (a) D The display is on when D = 1 and off when D = 0. Display data in the DDRAM is not affected and can be displayed immediately by setting D to logic 1. When the display is off (D = 0) the chip is in partial power-down mode: The LCD outputs are connected to VSS The LCD voltage generator and bias generator are turned off. Three oscillator cycles are required after sending the 'display off' instruction ensure all outputs are at VSS, afterwards OSC can be stopped, if the oscillator is running, the chip can still execute instructions. (b) C The cursor is displayed when C = 1 and inhibited when C = 0. The cursor is displayed using 5 dots in the 8th line (see Figure 1). (c) B B = 0, cursor character blink off. B = 1,the character indicated by the cursor blinks. The cursor character blink is displayed by switching between display characters and all dots on with a period of approximately 1 second. The cursor underline and the cursor character blink can be set to display simultaneously. 5. Function set (a) DL (Parallel mode only) Sets interface data width. Data is sent or received in bytes (DB7 to DB0) when DL = 1 or in two nibbles (DB7 to DB4) when DL = 0. When 4-bit width is selected, data is transmitted in two cycles using the parallel bus. In a 4-bit application DB3 to DB0 should be left opencircuit (internal pull-ups). Hence in the first `function set' instruction after power-on, M, SL and H are set to logic 1. A second `function set' must then be sent (2 nibbles) to set M, SL and H to their required values. I2C-bus interface set the DL bit to logic 1. (b) M Selects either 1-line by 32 display (M = 0) or 2-line by 16 display (M = 1).
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(c) SL Selects duty 1/9, 1-line by 16 display (independent of M and L). Only COMs 1 to 8 and 17 are to be used. All other COMs must be left open-circuit. The DDRAM map is the same as in the 2-line by 16 display mode, however, the second line is not displayable. (d) H When H = 0 the chip can be programmed via the standard 11 instruction codes. When H = 1 the extended range of instructions will be used. These are mainly for controlling the display configuration and the icons. 6. Cursor or display shift `Cursor/display shift' moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In 2-line displays, the cursor moves to the next line when it passes the last position (40) of the line. When the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. The Address Counter (AC) content does not change if the only action performed is shift display, but increments or decrements with the `cursor shift'. 7. Set CGRAM address `Set CGRAM address' sets bits 5 to 0 of the CGRAM address into the address counter (binary A5 to A0). Data can then be written to or read from the CGRAM. Attention: The CGRAM address uses the same address register as the DDRAM address and consists of 7 bits (binary A6 to A0). With the `set CGRAM address' command, only bits 5 to 0 are set. Bit 6 can be set using the `set DDRAM address' command first, or by using the auto-increment feature during CGRAM write. All bits 6 to 0 can be read using the `read busy flag' and `read address' command. When writing to the lower part of the CGRAM, ensure that bit 6 of the address is not set (e.g. by an earlier DDRAM write or read action). 8. Set DDRAM address `Set DDRAM address' sets the DDRAM address into the address counter (binary A6 to A0). Data can then be written to or read from the DDRAM. 9. Read busy flag and read address `Read busy flag' and `read address' read the Busy Flag (BF) and Address Counter (AC). BF = 1 indicates that an internal operation is in progress. The next instruction will not be executed until BF = 0. It is recommended that the BF status is checked before the next write operation is executed. At the same time, the value of the address counter expressed in binary A6 to A0 is read out. The address counter is used by both CGRAM and DDRAM, and its value is determined by the previous instruction. 10. Write data to CGRAM or DDRAM `Write data' writes binary 8-bit data D7 to D0 to the CGRAM or the DDRAM. Whether the CGRAM or DDRAM is to be written into is determined by the previous `set CGRAM address' or `set DDRAM address' command. Only bits D4 to D0 of CGRAM data are valid, bits D7 to D5 are `don't care'. After writing, the address automatically increments or decrements by 1, in accordance with the entry mode. 11. Read data from CGRAM or DDRAM `Read data' reads binary 8-bit data D7 to D0 from the CGRAM or DDRAM. The most recent `set address' command determines whether the CGRAM or DDRAM is to be read. The `read data' instruction gates the content of the Data Register (DR) to the bus while E is HIGH. After E goes LOW again, internal operation increments (or decrements) the AC and stores RAM data corresponding to the new AC into the DR. There are only three instructions that update the data register: `set CGRAM address' `set DDRAM address' `read data' from CGRAM or DDRAM. Other instructions do not modify the data register content.
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Extended instruction details explain H = 1, sets the chip into extended instruction set mode. 1. Icon control The NT7651 can drive up to 160 icons. See Figure 10 for CGRAM to icon mapping. (a) IM (Display mode) When IM = 0, the chip is in character mode. In the character mode characters and icons are driven (duty 1/18). The VLCD generator, if used, produces the VLCD voltage programmed in register VA. When IM = 1, the chip is in icon mode. In the icon mode only the icons are driven (duty 1/2) and the VLCD voltage generator, if used, produces the VLCD voltage as programmed in register VB. (b) IB (Icon blink control) Icon blink control is independent of the cursor and character blink function. When IB = 0, icon blink is disabled. Icon data is stored in CGRAM character 0 to 3 (4 x 5 x 8 = 160 bits for 160 icons). When IB = 1, icon blink is enabled. In this case each icon is controlled by two bits. Blink consists of two half phases (corresponding to the cursor character blink all on and normal display phases called even and odd phases hereafter). Icon states for the even phase are stored in CGRAM characters 0 to 3 (4 x 5 x 8 = 160 bits for 160 icons). These bits also define icon state when icon blink is not used. Icon states for the odd phase are stored in CGRAM character 4 to 7 (another 160 bits for the 160 icons). When icon blink is disabled CGRAM characters 4 to 6 may be used as normal CGRAM characters. 2. Screen configuration L Only in 1-line 32 characters display mode. Default is L = 0. L = 0: the two halves of a split screen are connected in a standard way. 1st 16characters of 32: segments are from 1to80, 2nd 16characters of 32: segments are from 1 to 80. L = 1: the two halves of a split screen are connected in a mirrored way. 1st 16characters of 32: segments are from 1to80, 2nd 16characters of 32: segments are from 80 to 1. This allows single layer PCB or glass layout. 3. Display configuration P, Q: default is P, Q = 0. P = 1: mirrors the segment data. Q = 1: mirrors the common data. 4. Temperature control Default is TC1 and TC2 = 0. This selects the default temperature coefficient for the internally generated VLCD. See Table 11. 5. Set VLCD The VLCD value is programmed by instruction. Two on-chip registers hold VLCD values for the character mode and the icon mode respectively (VA and VB). The generated VLCD value is independent of VDD, allowing battery operation of the chip. VLCD programming: 1. Send `function set' instruction with H = 1 2. Send `set VLCD ' instruction to write to voltage register: a) DB7, DB6 = 10: DB5 to DB0 are VLCD of character mode (VA) b) DB7, DB6 = 11: DB5 to DB0 are VLCD of icon mode (VB) c) DB5 to DB0 = 000000 Switches VLCD generator off (when selected) 3. Send `function set' instruction with H = 0 to resume normal programming. During `display off' and power-down the VLCD generator is also disabled. 6. Reducing current consumption Reducing current consumption can be achieved by one of the options given in Table 7. When VLCD lie outside the VDD range and must be generated, it is usually more efficient to use the onchip generator than an external regulator. Table 7 Reducing current consumption Original Mode Character mode Display on Any mode Alternative Mode icon mode (control bit IM) display off (control bit D) power-down (PD pad)
Table 8 Instruction set for I2C-bus commands CONTROL BYTE Co RS 0 0 0 0 0 COMMAND BYTE I2C-BUS COMMANDS
0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R/ W is set together with the slave address.
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Table 9 Instruction set with parallel bus commands Instruction RS R/ W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 H=0 or 1 NOP Function set 0 0 0 0 0 0 0 0 0 1 0 DL 0 0 0 M 0 SL 0 H no operation 3 3 Description Required clock cycles
Read busy flag and address counter Read data Write data
0
1
1 1
1 0
sets interface Data Length (DL) and number of display lines (M); single line/duty 1/9 (SL),extended instruction set control (H) BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 reads the Busy Flag (BF) indicating internal operating is being performed and reads address counter contents D7 D6 D5 D4 D3 D2 D1 D0 reads CGRAM or DDRAM data D7 D6 D5 D4 D3 D2 H=0 D1 D0 writes CGRAM or DDRAM data
0
3 3
Clear display Return home
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
1 0
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
Display control
0
0
0
0
0
0
1
D
C
B
Cursor /display shift Set CGRAM address Set DDRAM address Reserved Screen configuration Display configuration Icon control Temperature control Set VLCD
0 0
0 0
0 0
0 1
0 A5
1 A4
S/C R/L A3 A2
0 A1
0 A0
0
0
1
A6
A5
A4
A3
A2
A1
A0
clears entire display and sets DDRAM address counter =0 sets DDRAM address counter =0, also returns shifted display to original position, DDRAM contents remain unchanged sets cursor move direction and specifies shift of display, these operations are performed during data write and read sets entire display on/off (D), cursor on/off (C) and blink of cursor position character (B); D =0 (display off) puts chip into the power-down mode moves cursor and shifts display without changing DDRAM contents sets CGRAM address, bit 6 is to be set by the command `set DDRAM address' sets DDRAM address
165 165
3
3
3 3
3
H=1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 V 0 0 0 0 0 D5 0 0 0 0 1 D4 0 0 0 1 0 D3 0 0 1 IM 0 D2 0 1 P IB 1 L Q 0 do not use set screen configuration set display configuration set icon mode (IM), icon blink (IB) 3 3 3 3 3
TC1 TC2 set temperature coefficient (TCx) D1 D0 store VLCD in register VA or VB (V)
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Table 10 Explanations of symbols used in Table 9 Bit I/D S D C B S/C R/L DL H L (no impact, if M=1or SL =1) P Q decrement display freeze display off cursor off cursor character blink off: character at cursor position does not blink cursor move left shift 4bits use basic instruction set left/right screen: standard connection. 1st 16characters of 32: columns are from 1to80 2nd 16characters of 32: columns are from 1to80 segment data is displayed from 1 to 80. (column data: left to right) common data is displayed from COM1 to COM16 and icon common data is in COM17 and COM18. (row data: top to bottom/2 lines) character mode; full display icon blink disabled set VA State Logic0 increment display shift display on cursor on cursor character blink on: character at cursor position blinks display shift right shift 8bits use extended instruction set left/right screen: mirrored connection 1st 16characters of 32: columns are from 1to80 2nd 16characters of 32: columns are from 80to1 segment data is displayed from 80 to1 (column data: right to left) common data is displayed from COM16 to COM1 and icon common data is in COM18 and COM17. (row data: bottom to top/2 lines) icon mode; only icons displayed icon blink enabled set VB 2-line by 16display duty 1/9 (1 x 16 character display) another control byte follows after data or command. Logic1
IM IB V
M (no impact, 1-line by 32display if SL=1) SL Co duty 1/18 (1 x 32 or 2 x 16 character display) last control byte; see Table 8
Table 11 Explanations of TC1 and TC2 used in Table 9 TC1 0 1 0 1 TC2 0 0 1 1 Description VLCD temperature coefficient0, It is - 8.0 mV/K 2 mV/K (VLCD=5.0V) VLCD temperature coefficient1, It is - 9.0 mV/K 2 mV/K (VLCD=5.0V) VLCD temperature coefficient2, It is - 10.5 mV/K 2 mV/K (VLCD=5.0V) VLCD temperature coefficient3, It is - 11.8 mV/K 2 mV/K (VLCD=5.0V)
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display:
SEG 1 to 5
SEG 6 to 10
-----
SEG 76 to 80
COM17
1
2
3
4
5
6
7
8
9 10
-----
76 77 78 79 80
COM 18
81 82 83 84 85
86 87 88 89 90
-----
156 157 158 159 160
character codes icon no. phase COM/SEG 7 6 5 4 3 2 1 0
CGRAM address
CGRAM data 3 2 1 0 LSB 1 0 1 ... 1 1 1 0 ... 1 0 1 0 ... 0 1 1 0 0 0 1 0 ... 1 0 1 0 ... 0 1 1 1 0 0 ... icon view
65432104
MSB 1-5 6-10 11-15 ... 76-80 81-85 ... 156-160 1-5 ... 156-160 even even even ... even even ... even odd (blink) ... odd (blink) 17/1-5 17/6-10 17/11-15 ... 17/76-80 18/1-5 ... 18/76-80 17/1-5 ... 18/76-80 0 0 0 0 0 0 0 0 0 0 0 0 ... 0 1 1 0 0 0 0 0 0 0 0 ... 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ... 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
LSBMSB 0 0 0
LSBMSB 0 1 1
00000001 00000010 00000100 ...
1 0
00011111 00100001 ...
1 0
00111111 01000000 ...
1
01111110
Figure 10 CGRAM to icon mapping
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Interfaces to MPU
1. Parallel interface The NT7651 can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. In 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB7 to DB0. Three further control lines E, RS and R/ W are required. In 4-bit mode data is transferred in two cycles of 4 bits each using pads DB7 to DB4 for the transaction. The higher order bits (corresponding to DB7 to DB4 in 8-bit mode) are sent in the first cycle and the lower order bits (DB3 to DB0 in 8-bit mode) in the second. Data transfer is complete after two 4-bit data transfers. It should be noted that two cycles are also required for the busy flag check. 4-bit operation is selected by instruction, see Figure 12 to Figure 13 for examples of bus protocol. In 4-bit mode, pads DB3 to DB0 must be left opencircuit. They are pulled up to VDD internally. If the 4-bit interface is used without reading out from the chip (i.e. R/ W is set permanently to logic 0), the unused ports DB0 to DB3 can either be set to VSS1 or VDD1 instead of leaving them open-circuit. 2. I2C-bus interface The is for bidirectional, two-line communication between different ICs or modules. The two lines are the Serial Data line (SDA) and the Serial Clock Line (SCL). Both lines must be connected to a positive supply via pull-up resistors. Data transfer may be initiated only when the bus is not busy. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. I2C-bus The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. In the I2C-bus read mode, DB7 to DB1 should be connected to VDD1 or left open-circuit. (a) I2C-BUS Protocol Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the START procedure. The I2C-bus configuration for the different NT7651 read and write cycles is shown in Figure 14 to Figure 18. The slow down feature of the I2C-bus protocol (receiver holds SCL LOW during internal operations) is not used in the NT7651. (b) Definitions Transmitter: the device which sends the data to the bus Receiver: the device which receives the data from the bus Master: the device which initiates a transfer, generates clock signals and terminates a transfer Slave: the device addressed by a master Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted Synchronization: procedure to synchronize the clock signals of two or more devices. NT7651 slave address: 011101SA0.
MASTER TRANSMITTER /RECEIVER SDA
SLAVE RECEIVER
SLAVE TRANSMITTER /RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER /RECEIVER
SCL
Figure 11 System configuration.
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RS R/W E DB7 DB6 DB5 DB4
IR7 IR3 BF AC3 DR7 DR3
IR6
IR3
AC6
AC2
DR6
DR2
IR5
IR1
AC5
AC1
DR5
DR1
IR4
IR0
AC4
AC0
DR4
DR0
Figure 12 4-bit transfer
RS
R/W E internal
internal operation
DB7
data
Busy
Busy
not Busy
data instuction write
instuction write busy flag check busy flag check busy flag check
Figure 13 Busy flag checking timing sequence
SDA
SCL Start Stop
Figure 14 Definition of START and STOP conditions
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SCL from Master Data output tranamitter Data output receiver Start
Clock pulse for acknowledgement 1 2 8 9
not acknowledgement
acknowledgement
Figure 15 Acknowledgement on the I2C-bus
S
Slave 0 address(SA0)
A
1 RS
Control byte
A
Data byte
A
0 RS
Control byte
A
Data byte
A
P
R/W S = Start
Co P = Stop
Co A = Acknowledgement from NT7651
updata data pointer
Figure 16 Master transmits to slave receiver; write mode
S
Slave 0 address(SA0)
A
1 RS
Control byte
A
Data byte
A
0 RS
Control byte
A
Data byte
A
R/W
S
Co
A Data byte A
Co
no acknowledgement
Last data byte 1 P
Slave 1 address(SA0)
R/W S = Start
Co
updata data pointer
updata data pointer A = Acknowledgement
P = Stop
Figure 17 Master reads after setting word address; writes word address, set RS; `read data'
no acknowledgement
Slave S 1 address(SA0) A Data byte AM Last data byte 1 P
R/W
Co
updata data pointer
updata data pointer
S = Start
P = Stop
A = Acknowledgement from NT7651 AM = Acknowledgement from master
Figure 18 Master reads slave immediately after first byte; read mode (RS previously defined)
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Absolute Maximum Rating*
DC Supple Voltage . . . . . . . . . . . . . . -0.3V to +5.0V LCD Supple Voltage . . . . . . . . . . . . . -0.3V to +7.0V Input Voltage . . . . . . . . . . . . . . .. -0.3V to VDD+0.3V Input Voltage . . . . . . . . . . . . . . . -0.3V to VLCD+0.3V Operating Temperature . . . . . . . . . .-40C to +85C Storage Temperature . . . . . . . . . . .-55C to +125C *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics
VDD1 = VDD2 =3.0V, VLCD=5.0V, VSS1 = VSS2 = 0V, TA = 25C, fOSC=200KHz, unless otherwise specified Symbol VDD1 VDD2 VLCD IDD Parameter Operating voltage High voltage generator supply voltage LCD supply voltage Operating current Min. 1.5 2.2 4.5 - Typ. - - - 150 Max. 3.5 3.5 6.5 180 Unit V V V A Normal mode, DC-DC converter on, LCD outputs are open-circuit inputs at VDD or VSS Icon mode, DC-DC converter on, LCD outputs are open-circuit inputs at VDD or VSS Power-down mode, ISB2 Standby current 2 - - - - - - - - 4 -8 0.15 - 10 15 20 - -8.0 -9.0 -10.5 -11.8 2 0.3 x VDD1 VDD1 0.2 x VDD1 VDD1 VDD1 - 1.5 VDD1 - - 1 +1 30 40 130 340 -6.0 -7.0 -8.5 -9.8 A DB7 to DB0, RS and R/ W =1, OSC =0, E=0, PD= 1 E, RS, R/ W , DB7 to DB0, SA0, SDA, SCL E, RS, R/ W , DB7 to DB0, SA0, SDA, SCL PD, RESET PD, RESET OSC OSC VOL = 0.4V, DB7toDB0, SDA VOH =2.4V, DB7toDB0 VI =VSS, DB7to DB0, RS, R/ W VI =VDD or VSS, all input pads External VLCD=5.0V, IO=20A External VLCD=5.0V, IO=20A External VLCD, LCD outputs unload VLCD2=5.0V, load current IVLCD=5A LCD outputs open-circuit When internal VLCD generation Conditions
ISB1
Standby current 1
-
-
160
A
VIL1 VIH1 VIL2 VIH2 VIL3 VIH3 IOL IOH IPU IL RLCOM RLSEG VBIASTOL VLCDTOL TC0 TC1 TC2 TC3
Low-level input voltage High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level voltage Low-level output current High-level output current Pull-up current Leakage current Common output resistance Segment output resistance Bias voltage tolerance VLCD tolerance VLCD temperature coefficient VLCD temperature coefficient VLCD temperature coefficient VLCD temperature coefficient
0 0.7 x VDD1 0 0.8 x VDD1 0 VDD1 - 0.1 1.6 -1 0.04 -1 - - - - -10.0 -11.0 -12.5 -13.8
V V V V V V mA mA A A K K mV mV
mV/K VLCD=5.0V mV/K VLCD=5.0V mV/K VLCD=5.0V mV/K VLCD=5.0V
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AC Characteristics
VDD = 3.0V, VLCD=5.0V, VSS = 0V, TA = 25C, fOSC=200KHz, unless otherwise specified Symbol fFRAME fOSC fOSC(ext) tOSCST Parameter LCD frame frequency Oscillator frequency External clock frequency Oscillator start-up time Min. 65 190 140 - Typ. - - - 1 Max. 160 450 450 1.2 Unit Hz KHz KHz ms after power-down Conditions internal clock not available at any pad
Bus timing characteristics: parallel interface Write Operation (Writing DATA from MPU to NT7651) Tcy(en) tW(en) tSU(A) t h(A) tSU(D) t h(D) enable cycle time enable pulse width address set-up time address hold time data set-up time data hold time 500 220 50 25 60 25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 150 100 ns ns ns ns ns ns
Read Operation (Reading DATA from NT7651 to MPU) Tcy(en) tW(en) tSU(A) t h(A) t d(D) t h(D) fSCL t LOW t HIGH t SU;DAT t HD;DAT tr tf CB t SU;STA t HD;STA t SU;STO t SW enable cycle time enable pulse width address set-up time address hold time data delay time data hold time Timing characteristics: SCL clock frequency SCL clock low period SCL clock high period data set-up time data hold time SCL, SDA rise time SCL, SDA fall time capacitive bus line load set-up time for a repeated START condition START condition hold time set-up time for STOP condition tolerable spike width on bus 500 220 50 25 - 20 I2C-bus - 1.3 0.6 100 0 - - - 0.6 0.6 0.6 - ns ns ns ns ns ns
interface (input capacitance Ci = 10pF) 400 - - - - 300 300 400 - - - 50 KHz s s ns ns ns ns pF s s s ns
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Timing Characteristics
VIH1 VIL1 tSU(A) VIH1 VIL1 th(A)
RS
R/W
VIL1 tW (en) VIH1 VIL1 tSU(D) VIH1 VIL1 th(D)
VIL1
E
VIL1
DB[0:7]
VIH1 VIL1
data
VIH1 VIL1 Tcy(en)
Figure 19 Parallel bus writing data from MPU to NT7651
RS
VIH1 VIL1 tSU(A) VIH1
VIH1 VIL1 th(A) VIH1
R/W
tW (en) VIH1 VIL1 td(D) VIH1 VIL1 th(D) VIL1
E
DB[0:7]
VOH1 VOL1
data
VOH1 VOL1 Tcy(en)
Figure 20 Parallel bus reading data from NT7651 to MPU
tBUF SDA tHD;STA tHD;DAT tHIGH tf tSU;DAT
SCL tLOW tr
SDA tSU;STA tSU;STO
Figure 21 I2C-bus timing diagram.
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Application Information
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Bonding Diagram
5080m 142 143 83 82
NT7651
Y 1370m
(0,0)
X
ALK_L 162 1 62
ALK_R 63
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Preliminary
Designation SCL SCL DUMMY (VSS1) RESET PD SDA SDA R/ W RS T6 DB[0]/SA0 DB[1] DB[2] DB[3] DB[4] DB[5] DB[6] DB[7] T5 T4 OSC OSC VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD3 VDD3
X -1982.5 -1917.5 -1852.5 -1787.5 -1722.5 -1657.5 -1592.5 -1527.5 -1462.5 -1397.5 -1332.5 -1267.5 -1202.5 -1137.5 -1072.5 -1007.5 -942.5 -877.5 -812.5 -747.5 -682.5 -617.5 -552.5 -487.5 -422.5 -357.5 -292.5 -227.5 -162.5 -97.5
Y -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620
Pad No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 31/38
Designation VDD3 VDD3 VDD3 VDD3 E T1 T2 T3 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VLCD1 VLCD1 VLCD1 VLCD1 VLCD1 VLCD1 VLCD2 VLCD2 VLCD2 VLCD2
X -32.5 32.5 97.5 162.5 227.5 292.5 357.5 422.5 487.5 552.5 617.5 682.5 747.5 812.5 877.5 942.5 1007.5 1072.5 1137.5 1202.5 1267.5 1332.5 1397.5 1462.5 1527.5 1592.5 1657.5 1722.5 1787.5 1852.5
Y -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 Ver 0.21
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Bonding Diagram (continued)
Pad No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Designation VLCD2 VLCD2 COM[17] COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] COM[7] COM[8] COM17DUP SEG[80] SEG[79] SEG[78] SEG[77] SEG[76] SEG[75] SEG[74] SEG[73] SEG[72] SEG[71] SEG[70] SEG[69] SEG[68] SEG[67] SEG[66] SEG[65] SEG[64] SEG[63] SEG[62] SEG[61] SEG[60] SEG[59] SEG[58] SEG[57] SEG[56] SEG[55] SEG[54] SEG[53] X 1917.5 1982.5 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 1917.5 1852.5 1787.5 1722.5 1657.5 1592.5 1527.5 1462.5 1397.5 1332.5 1267.5 1202.5 1137.5 1072.5 1007.5 942.5 877.5 812.5 Y -620 -620 -617.5 -552.5 -487.5 -422.5 -357.5 -292.5 -227.5 -162.5 -97.5 -32.5 32.5 97.5 162.5 227.5 292.5 357.5 422.5 487.5 552.5 617.5 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 Pad No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 139 139 140 Designation SEG[52] SEG[51] SEG[50] SEG[49] SEG[48] SEG[47] SEG[46] SEG[45] SEG[44] SEG[43] SEG[42] SEG[41] SEG[40] SEG[39] SEG[38] SEG[37] SEG[36] SEG[35] SEG[34] SEG[33] SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] X 747.5 682.5 617.5 552.5 487.5 422.5 357.5 292.5 227.5 162.5 97.5 32.5 -32.5 -97.5 -162.5 -227.5 -292.5 -357.5 -422.5 -487.5 -552.5 -617.5 -682.5 -747.5 -812.5 -877.5 -942.5 -1007.5 -1072.5 -1137.5 -1202.5 -1267.5 -1332.5 -1397.5 -1462.5 -1527.5 -1592.5 -1657.5 -1722.5 -1787.5 Y 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620
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Bonding Diagram (continued)
Pad No. 141 142 143 144 145 146 147 148 149 150 151 152 Designation SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] SEG[1] X -1852.5 -1917.5 -2475 -2475 -2475 -2475 -2475 -2475 -2475 -2475 -2475 -2475 Y 620 620 617.5 552.5 487.5 422.5 357.5 292.5 227.5 162.5 97.5 32.5 Pad No. 153 154 155 156 157 158 159 160 161 162 Designation COM18DUP COM[16] COM[15] COM[14] COM[13] COM[12] COM[11] COM[10] COM[9] COM[18] ALK_L ALK_R X -2475 -2475 -2475 -2475 -2475 -2475 -2475 -2475 -2475 -2475 -2149 2149 Y -32.5 -97.5 -162.5 -227.5 -292.5 -357.5 -422.5 -487.5 -552.5 -617.5 -535 -535
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5080m 142 143 83 82
NT7651R
Y 1370m
(0,0)
X
ALK_L 162 1 62
ALK_R 63
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Designation SCL SCL DUMMY (VSS1) RESET PD SDA SDA R/ W RS T6 DB[0]/SA0 DB[1] DB[2] DB[3] DB[4] DB[5] DB[6] DB[7] T5 T4 OSC OSC VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD3 VDD3
X -1982.5 -1917.5 -1852.5 -1787.5 -1722.5 -1657.5 -1592.5 -1527.5 -1462.5 -1397.5 -1332.5 -1267.5 -1202.5 -1137.5 -1072.5 -1007.5 -942.5 -877.5 -812.5 -747.5 -682.5 -617.5 -552.5 -487.5 -422.5 -357.5 -292.5 -227.5 -162.5 -97.5
Y -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620
Pad No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Designation VDD3 VDD3 VDD3 VDD3 E T1 T2 T3 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VLCD1 VLCD1 VLCD1 VLCD1 VLCD1 VLCD1 VLCD2 VLCD2 VLCD2 VLCD2
X -32.5 32.5 97.5 162.5 227.5 292.5 357.5 422.5 487.5 552.5 617.5 682.5 747.5 812.5 877.5 942.5 1007.5 1072.5 1137.5 1202.5 1267.5 1332.5 1397.5 1462.5 1527.5 1592.5 1657.5 1722.5 1787.5 1852.5
Y -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620 -620
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Bonding Diagram (continued)
Pad No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Designation VLCD2 VLCD2 COM[17] COM[8] COM[7] COM[6] COM[5] COM[4] COM[3] COM[2] COM[1] COM17DUP SEG[80] SEG[79] SEG[78] SEG[77] SEG[76] SEG[75] SEG[74] SEG[73] SEG[72] SEG[71] SEG[70] SEG[69] SEG[68] SEG[67] SEG[66] SEG[65] SEG[64] SEG[63] SEG[62] SEG[61] SEG[60] SEG[59] SEG[58] SEG[57] SEG[56] SEG[55] SEG[54] SEG[53] X 1917.5 1982.5 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 2475 1917.5 1852.5 1787.5 1722.5 1657.5 1592.5 1527.5 1462.5 1397.5 1332.5 1267.5 1202.5 1137.5 1072.5 1007.5 942.5 877.5 812.5 Y -620 -620 -617.5 -552.5 -487.5 -422.5 -357.5 -292.5 -227.5 -162.5 -97.5 -32.5 32.5 97.5 162.5 227.5 292.5 357.5 422.5 487.5 552.5 617.5 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 Pad No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 139 139 140 Designation SEG[52] SEG[51] SEG[50] SEG[49] SEG[48] SEG[47] SEG[46] SEG[45] SEG[44] SEG[43] SEG[42] SEG[41] SEG[40] SEG[39] SEG[38] SEG[37] SEG[36] SEG[35] SEG[34] SEG[33] SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] X 747.5 682.5 617.5 552.5 487.5 422.5 357.5 292.5 227.5 162.5 97.5 32.5 -32.5 -97.5 -162.5 -227.5 -292.5 -357.5 -422.5 -487.5 -552.5 -617.5 -682.5 -747.5 -812.5 -877.5 -942.5 -1007.5 -1072.5 -1137.5 -1202.5 -1267.5 -1332.5 -1397.5 -1462.5 -1527.5 -1592.5 -1657.5 -1722.5 -1787.5 Y 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620 620
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Bonding Diagram (continued)
Pad No. 141 142 143 144 145 146 147 148 149 150 151 152 Designation SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] SEG[1] X -1852.5 -1917.5 -2475 -2475 -2475 -2475 -2475 -2475 -2475 -2475 -2475 -2475 Y 620 620 617.5 552.5 487.5 422.5 357.5 292.5 227.5 162.5 97.5 32.5 Pad No. 153 154 155 156 157 158 159 160 161 162 Designation COM18DUP COM[9] COM[10] COM[11] COM[12] COM[13] COM[14] COM[15] COM[16] COM[18] ALK_L ALK_R X -2475 -2475 -2475 -2475 -2475 -2475 -2475 -2475 -2475 -2475 -2149 2149 Y -32.5 -97.5 -162.5 -227.5 -292.5 -357.5 -422.5 -487.5 -552.5 -617.5 -535 -535
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Package Information
Chip Outline Dimensions
A2 A1 60mn A3 A2 A1
unit: m
C1 n m
C3
C1
A3
A3
NT7651/NT7651R
20nm m r (metal2) r m 20nm
m C2 C1 n B1 B2 B2 A3 C3 62mn B1 n n C2 C1
Symbol A1 A2 A3 B1 B2 C1
Dimensions in m 65 622.5 65 391 557.5 67.5
Symbol C2 C3 r m n
Dimensions in m 150 65 35 42 90
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Ordering Information
Part No. CGROM Code Stand code R NT7651H-BDT02 Stand code S Stand code R NT7651RH-BDT02 Stand code S Package COG FORM COG FORM COG FORM COG FORM
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